ASIC Engineer

À propos du poste

Uncharted Network is designing custom silicon to accelerate its market-data and order-matching pipelines, and we are looking for an experienced ASIC Engineer to own blocks from RTL through tape-out. You will work on designs targeting our most latency-sensitive paths — packet parsing, timestamp insertion, and deterministic arbitration logic — collaborating closely with the low-latency software team to define interfaces and validate the full system. We run FPGA prototypes in parallel and expect fluency across both domains. We want engineers who build reliable, verifiable hardware and who are as comfortable reviewing a timing report as they are writing a testbench.

Responsabilités

• Design and implement RTL blocks in SystemVerilog targeting market-data and execution-path ASIC designs
• Lead simulation-based and formal verification of assigned blocks using structured UVM testbenches and property checking
• Run synthesis and static timing analysis, iterating on timing closure with backend physical design teams
• Maintain and extend the FPGA prototype environment used for pre-tape-out system validation
• Define interface contracts with the low-latency software engineering team and participate in integration testing
• Write detailed design documentation and participate in specification and design-review processes

Exigences

• 5+ years of ASIC design experience, including at least one production tape-out from RTL through GDSII
• Expert-level SystemVerilog; deep familiarity with UVM or a comparable structured verification methodology
• Experience with synthesis flows (Synopsys DC or Cadence Genus) and STA (PrimeTime or Tempus)
• Ability to read and action timing closure reports with an understanding of setup/hold and multi-corner analysis
• Experience with FPGA tools (Xilinx Vivado or Intel Quartus) for prototype development and validation
• Strong written communication for specification documentation and design-review participation

Un plus

• Experience with formal verification tools (Jasper Gold, OneSpin, or SymbiYosys)
• Familiarity with embedded PCIe or Ethernet MAC/PHY layer implementations at the RTL level
• Background in hardware description using functional approaches (Hardcaml, Clash, or SpinalHDL)